This invention relates to Analog to Digital Converters (ADCs), particularly to electronic circuits for flash ADCs with accurate capacitive weighting, one clock cycle conversion, simple control, interchangeable inputs, and linear or nonlinear conversion.
Capacitance is the most accurate device in many Very Large Scale Integration (VLSI) processes. This is one of the reasons, that many ADCs use capacitors and the charge redistribution principle. The most compact architectures in the prior art perform the conversion in many steps, rather than in parallel to save hardware (for example U.S. Pat. No. 4,831,381, U.S. Pat. No. 4,517,549, U.S. Pat. No. 4,129,863, and U.S. Pat. No. 4,922,252). These ADCs are hardware efficient, but can not be used at very high speeds because many clock cycles are needed for the conversion.
Flash converters perform conversion in parallel, mostly in one clock cycle. Most of the n-bit architectures in the prior art use a resistive ladder with 2n resistors to generate a series of 2n reference voltages and 2n comparators in parallel to compare the input voltage to the plurality of the reference voltages. In these architectures the resistance of the switch which connects the resistive ladder to the reference voltage has to be taken into account. U.S. Pat. No. 4,742,330 discloses a capacitive flash ADC. This ADC performs 2n bit conversion using 2n parallel branches in three phases. In the first phase, offset cancellation takes place. In the second and the third phases the n-bit most significant bits (MSBs) and n-bit least significant bits (LSBs) are obtained respectively. The operation of the second phase is closely related to that of the classical flash ADC architecture with a resistive ladder which is described above. The MSBs determine the coarse range {Vi . . . , Vi+1} where the input signal lies. In the third phase, the LSBs are determined by dividing the coarse voltage range {Vi . . . Vi+1} into 2n fine voltage levels by using 2n parallel branches, each containing log2n binary weighted capacitors. Some of these capacitors are connected to Vi and others to Vi+1 to interpolate between the two extremities. The 2n comparators compare the input voltage to the generated 2n fine reference voltages in parallel.
A general feature of prior art ADC implementations is that the architectures are not symmetric with respect to the two input voltages, namely the reference voltage and the signal voltage that is being converted. In general, it is also assumed that the reference voltage is non-time-varying. In the following a principle is disclosed which overcomes these limitations
It is aim of the invention to provide an electronic circuit for a capacitive flash ADC which ameliorates or overcomes one or more of the disadvantages of known capacitive flash ADC circuits:
It would be desirable if:
the architecture of the circuit is symmetric with respect to the two input voltages, so the reference voltage and the signal voltage which is being converted are interchangeable during operation,
the reference voltage can be time-varying and moreover can have as high a frequency components as the signal voltage which is being converted,
it will benefit from computing with the most accurate elements of VLSI processes capacitors,
it will perform analog to digital conversion within one clock cycle, and
the architecture is simple to control.
The present invention consists in an electronic circuit for a capacitive flash analog to digital converter for converting the ratio of first and second analog signals into a digital code representation using an array of parallel capacitive comparator branches, each branch computing one bit of the digital code simultaneously according to its array index, wherein the first analog signal is applied as a voltage difference between first signal nodes comprising a first positive signal node and a first negative signal node, the second analog signal is applied as a voltage difference between second signal nodes comprising a second positive signal node and a second negative signal node, each branch comprising:
wherein the first and second positive capacitors also respectively have first and second positive opposite plates which are respectively switchably connected to the first and second signal nodes, and the first and second negative capacitors also respectively have first and second negative opposite plates which are respectively switchably connected to the first and second signal nodes.
Preferably the analog to digital conversion is performed within one clock cycle comprising a first and second phase.
Preferably the digital code is a digital thermometer code.
Preferably, in the first phase of the clock cycle, the first positive opposite plate is connected to the first positive signal node and the second positive opposite plate is connected to the second negative signal node, the first negative opposite plate is connected to the first negative signal node and the second negative opposite plate is connected to the second positive signal node, and the first feedback switch connects the negative output node to the positive input node of the comparator and the second feedback switch connects the positive output node to the negative input node of the comparator; and in the second phase of the clock cycle, the first positive opposite plate is connected to the first negative signal node and the second positive opposite plate is connected to the second positive signal node, the first negative opposite plate is connected to the first positive signal node and the second negative opposite plate is connected to the second negative signal node, and both first and second feedback switches are open, thereby outputting one bit of the digital code by the polarity of the voltage difference between the positive and negative output nodes of the comparator
Preferably the capacitances of the respective first positive, first negative, second positive and second negative capacitors are different for each branch according to the array index of that branch.
Preferably, in any one branch, the capacitance of the first positive capacitor substantially equals the capacitance of the first negative capacitor and the capacitance of the second positive capacitor substantially equals the capacitance of the second negative capacitor.
Preferably, in any one branch, the ratio of the capacitances of the first positive and second positive capacitors is a linear function of the array index of that branch, thereby providing a linear conversion between the ratio of the first and second analog signals and the digital code.
Alternatively it is preferred that, in any one branch, the ratio of the capacitances of the first positive and second positive capacitors is a nonlinear function of the array index of that branch, thereby providing a nonlinear conversion between the ratio of the first and second analog signals and the digital code.
Preferably the ratios of the capacitances of the respective capacitors in different branches are linearly spaced as a function of the array index.
Alternatively, it is preferred that the ratios of the capacitances of the respective capacitors in different branches are nonlinearly spaced as a function of the array index.
Preferably the first analog signal corresponds to the sine function of the phase angle of a periodic signal, the second analog signal corresponds to the cosine function of the phase angle of the periodic signal and, in any one branch, the ratio of the capacitances of first positive and second positive capacitors is a tangent function of a linear function of the array index of that branch, thereby providing a linear conversion between the phase angle and the digital code representation of this phase angle.